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OCTOBER 2003
ST16C1450/51
2.97V TO 5.5V UART
REV. 4.2.0
GENERAL DESCRIPTION
The ST16C1450, ST16C1451 series (here on denoted as the 145X) is a universal asynchronous receiver and transmitter (UART). The 145X is foot print compatible to the SSI 73M1550 and SSI 73M2550 UART with one byte FIFO and higher operating speed and lower access time. The 145X provides enhanced UART functions with a modem control interface, independent programmable baud rate generators with clock rates to 1.5 Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. An internal loopback capability allows onboard diagnostics. The 145X is available in a 28-pin PLCC/plastic-DIP 48-pin , TQFP packages. The Baud rate generator can be configured for either crystal or external clock input with the exception of the 28 pin 1451 package. An external clock must be provided for the 28 pin 1451 package. Each package type, with the exception of the 28 pin 1450, provides a buffered reset output that can be controlled through user software. The 145X is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. The ST16C145X is not compatible with the industry standard 16450 and will not work with the standard serial port driver in MS Windows (see pages 15-16 for details). For a MS Windows compatible UART, see the ST16C450.
FEATURES
* Pin and functionally compatible to SSI 73M1550/
2550
* 1 byte Transmit FIFO (THR) * 1 byte Receive FIFO with error tags (RHR) * Four levels of prioritized interrupts * Modem Control Signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
* Programmable character lengths (5, 6, 7, 8) with
even, odd or no parity
* Crystal or external clock input (except 28 pin
ST16C1451, external clock only)
* 1.5 Mbps Transmit/Receive operation (24 MHz)
with programmable clock control
* Power Down Mode (50 uA at 3.3 V, 200 uA at 5 V) * Software controllable reset output * 2.97 to 5.5 Volt operation
APPLICATIONS
* Battery Operated Electronics * Internet Appliances * Handheld Terminal * Personal Digital Assistants * Cellular Phones DataPort
FIGURE 1. BLOCK DIAGRAM
T HR A 2:A0 D 7:D0 IO R # IO W # C S# D ata Bu s In te rfac e D TR # , R T S # U A RT C on figu ra tion R eg s M o de m C on tro l S ig na ls D SR # , C T S #, C D #, RI# T ra ns m itter TX
IN T
R ec e ive r RHR
RX
B au d R ate G e n erator R ES E T R ST X TA L 1/CL K X TA L 2
C ry stal O sc /B u ffe r
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
ST16C1450/51 2.97V TO 5.5V UART FIGURE 2. ST16C1450 PINOUTS
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48-TQFP PACKAGE
DSR# VCC N.C. N.C. N.C. CD# N.C. N.C. D3 D2 D1 D0
NOTE: PINOUTS NOT TO SCALE.
ACTUAL SIZE OF TQFP PACKAGE IS SMALLER THAN PLCC PACKAGE.
48
47
46
45
44
43
42
41
40
39
38
N.C. N.C. D4 D5 D6 D7 RX TX CS# N.C. N.C. N.C.
1 2 3 4 5 6
37 36 35 34 33 32 31
N.C. N.C. CTS# RESET DTR# RTS# A0 N.C. A1 A2 N.C. N.C.
ST16C1450CQ48
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 29 28 27 26 25
28-PDIP PACKAGES
D0 D1 D2 D3 D4 1 2 3 4 28 27 26 25 VCC CD# DSR# CTS# RESET DTR# RTS# A0 A1 A2 INT RI# IOR# GND
XTAL1
XTAL2
RST
N.C.
N.C.
N.C.
GND
IOW#
IOR#
N.C.
RI#
INT
5 6 7 8 9 10 11 12 13 14
ST16C1450CP28
24 23 22 21 20 19 18 17 16 15
28-PLCC PACKAGES
26 DSR# VCC D3 D2 D1 D0 CD#
D5 D6 D7 RX
28
27
4
3
2
1
D4 D5 D6 D7 RX TX
5 6 7 8 9 10
25 24 23
CTS# RESET DTR# RTS# A0 A1 A2
TX CS# XTAL1 XTAL2 IOW#
ST16C1450CJ28
22 21 20 19
CS# 11 12 13 14 15 16 17 RI# 18 INT
XTAL1
XTAL2
GND
IOW#
IOR#
2
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ST16C1450/51 2.97V TO 5.5V UART
FIGURE 3. ST16C1451 PINOUTS 48-TQFP PACKAGE
NOTE: PINOUTS NOT TO SCALE.
DSR#
ACTUAL SIZE OF TQFP PACKAGE IS SMALLER THAN PLCC PACKAGE.
VCC
N.C.
N.C.
N.C.
CD#
N.C. 38
48
47
46
45
44
43
42
41
40
39
N.C. N.C. D4 D5 D6 D7 RX TX CS# N.C. N.C. N.C.
1 2 3 4 5 6
37 36 35 34 33 32 31
N.C.
D3
D2
D1
D0
N.C. N.C. CTS# RESET DTR# RTS# A0 N.C. A1 A2 N.C. N.C.
ST16C1451CQ48
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 29 28 27 26 25
28-PDIP PACKAGES
D0 D1 1 2 3 4 28 27 26 25 VCC CD# DSR# CTS# RESET DTR# RTS# A0 A1 A2 INT RST RI# IOR#
XTAL1
XTAL2
RST
N.C.
N.C.
N.C.
GND
IOW#
IOR#
N.C.
RI#
INT
D2 D3 D4 D5
5 6 7 8 9 10 11 12 13 14
ST16C1451CP28
24 23 22 21 20 19 18 17 16 15
28-PLCC PACKAGES
26 DSR# VCC CD# D3 D2 D1 D0
D6 D7 RX TX
28
D4 D5 D6 D7 RX TX
27
4
3
2
1
5 6 7 8 9 10
25 24 23
CTS# RESET DTR# RTS# A0 A1 A2
CS# CLK IOW# GND
ST16C1451CJ28
22 21 20 19
CS# 11 12 IOW# 13 14 15 16 17 RST 18 INT
CLK
GND
IOR#
RI#
3
ST16C1450/51 2.97V TO 5.5V UART
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ORDERING INFORMATION
PART NUMBER ST16C1450CP28 ST16C1450CJ28 ST16C1450CQ48 ST16C1451CP28 ST16C1451CJ28 ST16C1451CQ48 ST16C1450IP28 ST16C1450IJ28 ST16C1450IQ48 ST16C1451IP28 ST16C1451IJ28 ST16C1451IQ48 PACKAGE 28-Lead PDIP 28-Lead PLCC 48-Lead TQFP 28-Lead PDIP 28-Lead PLCC 48-Lead TQFP 28-Lead PDIP 28-Lead PLCC 48-Lead TQFP 28-Lead PDIP 28-Lead PLCC 48-Lead TQFP OPERATING TEMPERATURE RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C DEVICE STATUS Discontinued. See the ST16C1450CQ48 for a replacement. Active Active Discontinued. See the ST16C1450CQ48 for a replacement. Discontinued. See the ST16C1450CQ48 for a replacement. Discontinued. See the ST16C1450CQ48 for a replacement.
-40C to +85C Discontinued. See the ST16C1450IQ48 for a replacement. -40C to +85C Active -40C to +85C Active -40C to +85C Discontinued. See the ST16C1450IQ48 for a replacement. -40C to +85C Discontinued. See the ST16C1450IQ48 for a replacement. -40C to +85C Discontinued. See the ST16C1450IQ48 for a replacement.
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ST16C1450/51 2.97V TO 5.5V UART
PIN DESCRIPTIONS
NAME 28-PIN 28-PIN 28-PIN PDIP PDIP PLCC (1450) (1451) (1450) 28-PIN PLCC (1451) 48-PIN TQFP (145X) TYPE DESCRIPTION
DATA BUS INTERFACE
A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 IOR# 21 20 19 1 2 3 4 5 6 7 8 16 21 20 19 1 2 3 4 5 6 7 8 15 21 20 19 1 2 3 4 5 6 7 8 16 21 20 19 1 2 3 4 5 6 7 8 15 30 28 27 43 45 46 47 3 4 5 6 20 I Address data lines [2:0]. A2:A0 selects internal UART's configuration registers.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/Output Read (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], places it on the data bus to allow the host processor to read it on the leading edge. Input/Output Write (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines [A2:A0]. Chip Select input (active low). A logic 0 on this pin selects the ST16C145X device. Interrupt Output (three-state, active high). INT output defaults to three-state mode and becomes active high when MCR bit-3 is set to a logic 1. INT output becomes a logic high level when interrupts are enabled in the interrupt enable register (IER), and whenever the transmitter, receiver, line and/or modem status register has an active condition.
IOW#
14
13
14
13
17
I
CS# INT
11 18
11 18
11 18
11 18
9 23
I O
MODEM OR SERIAL I/O INTERFACE
TX 10 10 10 10 8 O Transmit Data. This output is associated with individual serial transmit channel data from the 145X. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Receive Data. This input is associated with individual serial channel data to the 145X. Normal received data input idles at logic 1 condition. This input must be connected to its idle logic state, logic 1, else the receiver may report "receive break" and/or "error" condition(s).
RX
9
9
9
9
7
I
5
ST16C1450/51 2.97V TO 5.5V UART
28-PIN 28-PIN 28-PIN PDIP PDIP PLCC (1450) (1451) (1450) 22 22 22 28-PIN PLCC (1451) 22 48-PIN TQFP (145X) 31
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NAME
TYPE
DESCRIPTION
RTS#
O
Request to Send or general purpose output (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, leave it unconnected. Clear to Send or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC. Data Terminal Ready or general purpose output (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, leave it unconnected. Data Set Ready input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC. Carrier Detect input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC. Ring Indicator input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC.
CTS#
25
25
25
25
34
I
DTR#
23
23
23
23
32
O
DSR#
26
26
26
26
39
I
CD#
27
27
27
27
40
I
RI#
17
16
17
16
21
I
ANCILLARY SIGNALS
CLK 12 12 I External Clock Input. This function is associated with 28 pin PDIP and 28 pin PLCC ST16C1451 packages only. An external clock must be connected to this pin to clock the baud rate generator and internal circuitry. Crystal or external clock input. See Figure 4 for typical oscillator connections. Crystal or buffered clock output. See Figure 4 for typical oscillator connections. Reset Input (active high). When it is asserted, the UART configuration registers are reset to default values, see Table 6. Reset Output (active high). This output is only available on the ST16C1451. When IER bit-5 is a logic 0, RST will follow the logical state of the RESET pin. When IER bit-5 is a logic 1, the user may send software (soft) resets via MCR bit-2. Soft resets from MCR bit-2 are "ORed" with the state of the RESET pin.
XTAL1 XTAL2 RESET
12 13 24
24
12 13 24
24
15 16 33
I O I
RST
-
17
-
17
22
O
VCC
28
28
28
28
41
Pwr Power supply input of 2.97 to 5.5V.
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ST16C1450/51 2.97V TO 5.5V UART
28-PIN PLCC (1451) 14 48-PIN TQFP (145X) 19 1, 2, 10-14, 18, 24-26, 29, 35-38, 42, 44, 48
NAME
28-PIN 28-PIN 28-PIN PDIP PDIP PLCC (1450) (1451) (1450) 15 14 15 -
TYPE
DESCRIPTION
GND N.C.
Pwr Power supply common ground. Not connected.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION The ST16C145X provides serial asynchronous receive data synchronization, parallel-to-serial and serial-toparallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required in digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The 145X is capable of operation up to 1.5 Mbps with a 24 MHz crystal or external clock input with a 16X sampling clock (at VCC = 5.0V). With a crystal of 14.7456 MHz and through a software option, the user can select data rates up to 921.6 Kbps. 2.0 FUNCTIONAL DESCRIPTIONS 2.1 Internal Registers
The 145X has a set of enhanced registers for controlling, monitoring and data loading and unloading. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpad register (SPR). All the register functions are discussed in full detail later in "Section 3.0, UART INTERNAL REGISTERS" on page 13.
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ST16C1450/51 2.97V TO 5.5V UART 2.2 Crystal Oscillator or External Clock
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The 145X includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see "Section 2.3, Programmable Baud Rate Generator" on page 8. The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For further reading on oscillator circuit please see application note DAN108 on EXAR's web site. FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2 R1 0-120 (Optional)
R2 500K - 1M Y1
1.8432 MHz to 24 MHz
C1 22-47pF
C2 22-47pF
2.3
Programmable Baud Rate Generator
The UART has its own Baud Rate Generator (BRG). The BRG divides the input crystal or external clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG must be programmed during initialization to the operating data rate. Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the operating data rate. Table 1 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X clock rate. When using a non-standard data rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
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TABLE 1: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate 400 2400 4800 9600 19.2k 38.4k 76.8k 153.6k 230.4k 460.8k 921.6k DIVISOR FOR 16x Clock (Decimal) 2304 384 192 96 48 24 12 6 4 2 1 DIVISOR FOR 16x Clock (HEX) 900 180 C0 60 30 18 0C 06 04 02 01 DLM PROGRAM VALUE (HEX) 09 01 00 00 00 00 00 00 00 00 00 DLL PROGRAM VALUE (HEX) 00 80 C0 60 30 18 0C 06 04 02 01 DATA RATE ERROR (%) 0 0 0 0 0 0 0 0 0 0 0
2.4
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 2.4.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 2.4.2 Transmitter Operation The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
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ST16C1450/51 2.97V TO 5.5V UART FIGURE 5. TRANSMITTER OPERATION
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Data Byte
Transmit Holding Register (THR)
THR Interrupt (ISR bit-1) Enabled by IER bit-1
16X Clock Transmit Shift Register (TSR)
M S B
L S B
TXNOFIFO1
2.5
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a characterThe RHR interrupt is enabled by IER bit-0. 2.5.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. When there is data in the RHR register, the 3 error tags in LSR register (bits 2-4) indicates if there are any errors associated with that byte.
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ST16C1450/51 2.97V TO 5.5V UART
FIGURE 6. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock Receive Data Shift Register (RSR) Data Bit Validation
Receive Data Characters
Receive Data Byte and Errors
Error Tags in LSR bits 4:2
Receive Data Holding Register (RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
2.6
Special (Enhanced Feature) Mode
The 145X supports the standard features of the ST16C450. In addition the 145X supports some enhanced features not available for the ST16C450. These features are enabled by IER bit-5 and include a software controllable (SOFT) reset, power down feature and FIFO monitoring bits. 2.6.1 Soft Reset Soft resets are useful when the user desires the capability of resetting an externally connected device only. MCR bit-2 can be used to initiate a SOFT reset at the RST output pin. This does not reset the 145X (only the RESET input pin can reset the 145X). Soft resets from MCR bit-2 are "ORed" with the RESET input pin. Therefore both reset types will be seen at the RST output pin. 2.6.2 Power Down Mode The power down feature (controlled by MCR bit-7) provides the user with the capability to conserve power when the package is not in actual use without destroying internal register configuration data. This allows quick turnarounds from power down to normal operation. 2.7 Internal Loopback The 145X UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 7 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback test else upon exiting the loopback test the UART may detect and report a false "break" signal.
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ST16C1450/51 2.97V TO 5.5V UART FIGURE 7. INTERNAL LOOPBACK
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VCC TX Transmit Shift Register
MCR bit-4=1 Internal Data Bus Lines and Control Signals
Receive Shift Register RX VCC RTS# Modem / General Purpose Control Logic RTS#
CTS# VCC DTR#
CTS# DTR#
DSR#
DSR#
OP1# RI# RI#
OP2#
CD#
CD#
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3.0 UART INTERNAL REGISTERS The 145X has a set of configuration registers selected by address lines A0, A1 and A2. The 16C450 compatible registers can be accessed when LCR[7] = 0 and the baud rate generator divisor registers can be accessed when LCR[7] = 1. The complete register set is shown on Table 2 and Table 3. TABLE 2: ST16C145X UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES 0 00 REGISTER RHR - Receive Holding Register THR - Transmit Holding Register DLL - Div Latch Low Byte DLM - Div Latch High Byte IER - Interrupt Enable Register ISR - Interrupt Status Register Reserved LCR - Line Control Register MCR - Modem Control Register LSR - Line Status Register Reserved MSR - Modem Status Register Reserved SPR - Scratch Pad Register READ/WRITE Read-only Write-only Read/Write LCR[7] = 1 0 0 0 01 01 10 Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Write-only LCR[7] = 0 1 10 Read-only Write-only Read/Write LCR[7] = 0 COMMENTS LCR[7] = 0
0
00
0 1 1
11 00 01
1
11
13
ST16C1450/51 2.97V TO 5.5V UART
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TABLE 3: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS A2-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers 000 000 001 RHR THR IER RD WR RD/WR Bit-7 Bit-7 0 Bit-6 Bit-6 0 Bit-5 Bit-5 Special Mode Enable
(Enable MCR bits 7, 2)
Bit-4 Bit-4 0
Bit-3 Bit-3 Modem Status Int. Enable
Bit-2 Bit-2
Bit-1 Bit-1
Bit-0 Bit-0
RX Line TX RX Status Empty Data Int. Int. Int. Enable Enable Enable
LCR[7] = 0
010
ISR
RD
0
0
0
0
INT Source Bit-3 Parity Enable
INT INT INT Source Source Source Bit-2 Bit-1 Bit-0 Stop Bits Word Word Length Length Bit-1 Bit-0
011
LCR
RD/WR
Divisor Enable
Set TX Break
Set Parity 0
Even Parity
100
MCR
RD/WR
0/ Power Down Mode
0
Internal Loopback Enable RX Break
(OP2#)/ (OP1#)/ RTS# DTR# INT Output Output SOFT Control Control Output Reset Enable RX Framing Error Delta CD# Bit-3 RX Parity Error Delta RI# Bit-2 RX Overrun Error Delta DSR# Bit-1 RX Data Ready Delta CTS# Bit-0
101
LSR
RD
0
THR & TSR Empty RI# Input Bit-6
THR Empty
LCR[7] = 0
110 111
MSR SPR
RD RD/WR
CD# Input Bit-7
DSR# Input Bit-5
CTS# Input Bit-4
Baud Rate Generator Divisor 000 001 DLL DLM RD/WR RD/WR Bit-7 Bit-7 Bit-6 Bit-6 Bit-5 Bit-5 Bit-4 Bit-4 Bit-3 Bit-3 Bit-2 Bit-2 Bit-1 Bit-1 Bit-0 LCR[7] = 1 Bit-0
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4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 4.2 4.3 Receive Holding Register (RHR) - Read- Only Transmit Holding Register (THR) - Write-Only Interrupt Enable Register (IER) - Read/Write See "Receiver" on page 10. See "Transmitter" on page 9. The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character.
* Logic 0 = Disable the receive data ready interrupt (default). * Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable This bit enables the Transmit Ready interrupt which is issued whenever the THR is empty. If the THR is empty when this bit is enabled, an interrupt will be generated. Note that this interrupt does not behave in the same manner as the industry standard 16C550. See "Interrupt Clearing:" on page 16.
* Logic 0 = Disable Transmit Ready interrupt (default). * Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in the RHR.
* Logic 0 = Disable the receiver line status interrupt (default). * Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
* Logic 0 = Disable the modem status register interrupt (default). * Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved IER[5]: Special Mode Enable
* Logic 0 = Disable special mode functions (default). * Logic 1 = Enable special mode functions in addition to basic ST16C1450 functions. Enables ISR bits 4-5
(TXRDY/RXRDY), MCR bit-2 (soft reset) and MCR bit-7 (power down) functions. IER[7:6]: Reserved 4.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 4, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels.
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ST16C1450/51 2.97V TO 5.5V UART 4.4.1 Interrupt Generation:
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REV. 4.2.0
* LSR is by any of the LSR bits 1, 2, 3 and 4. * RXRDY is by received data in RHR. * TXRDY is by THR empty. * MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2 Interrupt Clearing:
* LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptied or cleared from RHR).
* RXRDY interrupt is cleared by reading RHR. * TXRDY interrupt is cleared by a read to the ISR register AND disabling the TXRDY interrupt (set IER bit-1 =
0), or by loading data into the TX FIFO.
* MSR interrupt is cleared by a read to the MSR register.
]
TABLE 4: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL ISR REGISTER STATUS BITS BIT-3 1 2 3 4 0 0 0 0 0 BIT-2 1 1 0 0 0 BIT-1 1 0 1 0 0 BIT-0 0 0 0 0 1 LSR (Receiver Line Status Register) RXRDY (Received Data Ready) TXRDY (Transmit Ready) MSR (Modem Status Register) None (default) SOURCE OF INTERRUPT
ISR[0]: Interrupt Status
* Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
* Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 4). ISR[7:4]: Reserved 4.5 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register.
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ST16C1450/51 2.97V TO 5.5V UART
LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received.
BIT-1 0 0 1 1 BIT-0 0 1 0 1 WORD LENGTH 5 (default) 6 7 8
LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2 0 1 1 WORD
LENGTH
STOP BIT LENGTH (BIT TIME(S)) 1 (default) 1-1/2 2
5,6,7,8 5 6,7,8
LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 5 for parity selection summary below.
* Logic 0 = No parity. * Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
* Logic 0 = ODD Parity is generated by forcing an odd number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format (default).
* Logic 1 = EVEN Parity is generated by forcing an even number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format.
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ST16C1450/51 2.97V TO 5.5V UART LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
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REV. 4.2.0
* LCR[5] = logic 0, parity is not forced (default). * LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. * LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 5: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3 X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, "1" Forced parity to space, "0"
LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a "space', logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
* Logic 0 = No TX break condition (default). * Logic 1 = Forces the transmitter output (TX) to a "space", logic 0, for alerting the remote receiver of a line
break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable.
* Logic 0 = Data registers are selected (default). * Logic 1 = Divisor latch registers are selected.
4.6 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output.
* Logic 0 = Force DTR# output to a logic 1 (default). * Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output.
* Logic 0 = Force RTS# output to a logic 1 (default). * Logic 1 = Force RTS# output to a logic 0.
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ST16C1450/51 2.97V TO 5.5V UART
MCR[2]: OP1# Output/Soft Reset OP1# is not available as an output pin on the 145X. But it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
* Logic 0 = OP1# output (RI# input) is at logic 1 (default). * Logic 1 = OP1# output (RI# input) is at logic 0.
In normal operation, this bit is associated with the RST (buffered reset) output pin. The logical state of the RST pin will follow exactly the logical state of the RESET pin. When IER bit-5 = 1, soft resets from MCR bit-2 are ORed with the state of the RESET input pin. Therefore both reset types will be seen at the RST pin. Note that asserting MCR bit-2 does not reset the 145X.
* Logic 0 = The RST output pin is a logic 0 (default). * Logic 1 = The RST output pin is a logic 1.
MCR[3]: OP2# or INT Output Enable When not in Internal Loopback Mode:
* Logic 0 = INT output is three-state (default). * Logic 1 = INT output is active high.
OP2# is not available as an output pin on the 145X. But it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem CD# interface signal.
* Logic 0 = OP2# output (CD# input) is a logic 1 (default). * Logic 1 = OP2# output (CD# input) is a logic 0.
MCR[4]: Internal Loopback Enable
* Logic 0 = Disable loopback mode (default). * Logic 1 = Enable local loopback mode, see loopback section and Figure 7.
MCR[6:5]: Reserved MCR[7]: Power Down Enable This bit can only be accessed when IER bit-5 = 1.
* Logic 0 = Normal mode (default). * Logic 1 = Power down mode. See "Power Down Mode" on page 11.
4.7 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic 1, an LSR interrupt will be generated when the character that is in the RHR has an error (parity, framing, overrun, break). LSR[0]: Receive Data Ready Indicator
* Logic 0 = No data in receive holding register (default). * Logic 1 = Data has been received and is saved in the receive holding register.
LSR[1]: Receiver Overrun Error Flag
* Logic 0 = No overrun error (default). * Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the RHR, therefore the data in the RHR is not corrupted by the error.
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ST16C1450/51 2.97V TO 5.5V UART LSR[2]: Receive Data Parity Error Tag
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REV. 4.2.0
* Logic 0 = No parity error (default). * Logic 1 = Parity error. The received character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. LSR[3]: Receive Data Framing Error Tag
* Logic 0 = No framing error (default). * Logic 1 = Framing error. The received character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. LSR[4]: Receive Break Error Tag
* Logic 0 = No break condition (default). * Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time).
LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. LSR[7]: Reserved 4.8 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general purpose inputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag
* Logic 0 = No change on CTS# input (default). * Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3). MSR[1]: Delta DSR# Input Flag
* Logic 0 = No change on DSR# input (default). * Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag
* Logic 0 = No change on RI# input (default). * Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[3]: Delta CD# Input Flag
* Logic 0 = No change on CD# input (default). * Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[4]: CTS Input Status
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REV. 4.2.0
ST16C1450/51 2.97V TO 5.5V UART
CTS# (active high, logical 1). Normally this bit is the compliment of the CTS# input. In the loopback mode, this bit is equivalent to bit-1 in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. MSR[5]: DSR Input Status DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to bit-0 in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.9 Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. TABLE 6: UART RESET CONDITIONS
REGISTERS DLL DLM RHR THR IER ISR LCR MCR LSR MSR Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0x00 Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF RESET STATE
SPR
I/O SIGNALS TX RTS# DTR# RST INT Logic 1 Logic 1 Logic 1 Logic 1
RESET STATE
Three-State Condition
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ST16C1450/51 2.97V TO 5.5V UART
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REV. 4.2.0
ABSOLUTE MAXIMUM RATINGS
Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation 7 Volts GND-0.3 V to 7 V -40o to +85oC -65o to +150oC 500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: 15%)
Thermal Resistance (48-TQFP) Thermal Resistance (28-PDIP) Thermal Resistance (28-PLCC) theta-ja = 59oC/W, theta-jc = 16oC/W theta-ja = 57oC/W, theta-jc = 23oC/W theta-ja = 55oC/W, theta-jc = 28oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V
SYMBOL PARAMETER LIMITS 3.3V MIN MAX -0.3 2.4 -0.3 2.0 0.6 VCC 0.8 VCC LIMITS 5.0V MIN MAX -0.5 3.0 -0.5 2.2 0.6 VCC 0.8 VCC 0.4 0.4 2.4 2.0 10 10 5 1.3 50 10 10 5 3 200 UNITS CONDITIONS
VILCK VIHCK VIL VIH VOL VOL VOH VOH IIL IIH CIN ICC IPWRDN
Clock Input Low Level Clock Input High Level Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Input Pin Capacitance Power Supply Current Power Down Current
V V V V V V V V uA uA pF mA uA See Test 1 IOL = 6 mA IOL = 4 mA IOH = -6 mA IOH = -1 mA
Test 1: The following inputs should remain steady at VCC or GND state to minimize Power Down current: A0-A2, D0-D7, IOR#, IOW#, CS# and modem inputs. Also, RX input must idle at logic 1 state while in Power Down mode.
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REV. 4.2.0
ST16C1450/51 2.97V TO 5.5V UART
AC ELECTRICAL CHARACTERISTICS TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V
SYMBOL PARAMETER LIMITS 3.3V MIN MAX 63 8 5 10 50 35 40 35 0 40 20 5 50 40 40 1 45 45 8 40 1 216-1 24 8 40 1 216-1 25 0 25 15 5 40 35 35 1 40 40 24 0 5 40 25 30 25 15 LIMITS 5.0V MIN 21 24 MAX ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Bclk ns ns Bclk ns Hz 100 pF load 100 pF load 100 pF load 100 pF load UNIT CONDITIONS
CLK OSC TAS TAH TCS TRD TDY TRDV TDD TWR TDS TDH TWDO TMOD TRSI TSSI TRRI TSI TINT TRST N Bclk
Clock Pulse Duration Oscillator/External Clock Frequency Address Setup Time Address Hold Time Chip Select Width IOR# Strobe Width Read/Write Cycle Delay Data Access Time Data Disable Time IOW# Strobe Width Data Setup Time Data Hold Time Delay From IOW# To Output Delay To Set Interrupt From MODEM Input Delay To Reset Interrupt From IOR# Delay From Stop To Set Interrupt Delay From IOR# To Reset Interrupt Delay From Stop To Interrupt Delay From Initial INT Reset To Transmit Start Reset Pulse Width Baud Rate Divisor Baud Clock
16X of data rate
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ST16C1450/51 2.97V TO 5.5V UART FIGURE 8. CLOCK TIMING
CLK CLK
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REV. 4.2.0
EXTERNAL CLOCK OSC
FIGURE 9. MODEM INPUT/OUTPUT TIMING
IOW# IOW
Active T WDO
RTS# DTR#
Change of state
Change of state
CD# CTS# DSR# T MOD INT
Change of state
Change of state
T MOD Active T RSI Active Active
IOR# IOR
Active
Active
Active T MOD
RI#
Change of state
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ST16C1450/51 2.97V TO 5.5V UART
FIGURE 10. DATA BUS READ TIMING
A0A2 TAS CS2#
Valid Address TAH TCS TDY TAS
Valid Address TAH TCS
IOR#
TRD
TRD
TRDV D0-D7 Valid Data
TDD
TRDV Valid Data
TDD
FIGURE 11. DATA BUS WRITE TIMING
A0A2 TAS CS2#
Valid Address TAH TCS TDY TAS
Valid Address TAH TCS
IOW#
TWR
TWR
TDS D0-D7 Valid Data
TDH
TDS Valid Data
TDH
25
ST16C1450/51 2.97V TO 5.5V UART FIGURE 12. RECEIVE READY & INTERRUPT TIMING
RX
Start Bit Stop Bit TSSR 1 Byte in RHR TSSR
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REV. 4.2.0
D0:D7
D0:D7 TSSR 1 Byte in RHR TSSR
D0:D7 TSSR 1 Byte in RHR TSSR
INT
RXRDY (ISR bit-5)
Active Data Ready TRR
Active Data Ready TRR
Active Data Ready TRR
IOR#
(Reading data out of RHR)
RXNFM
FIGURE 13. TRANSMIT READY & INTERRUPT TIMING
TX
(Unloading) Start Bit IER[1] enabled Stop Bit IER[1] enabled
D0:D7
D0:D7
D0:D7 IER[1] enabled
INT cleared*
INT cleared*
INT cleared*
INT*
TSRT
TSRT
TSRT
TXRDY (ISR bit-4)
TWT TWT TWT
IOW#
(Loading data into THR)
*INT is cleared when the ISR is read and IER[1] is disabled.
TXNonFIFO
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REV. 4.2.0
ST16C1450/51 2.97V TO 5.5V UART
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D D1 36 25
37
24
D1
D
48
13
1 B A2 e
1 2
C A Seating Plane A1 L
Note: The control dimension is the millimeter column
INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.039 0.002 0.037 0.007 0.004 0.346 0.272 MAX 0.047 0.006 0.041 0.011 0.008 0.362 0.280 MILLIMETERS MIN 1.00 0.05 0.95 0.17 0.09 8.80 6.90 MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10
0.020 BSC 0.018 0 0.030 7
0.50 BSC 0.45 0 0.75 7
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ST16C1450/51 2.97V TO 5.5V UART
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REV. 4.2.0
PACKAGE DIMENSIONS (28 PIN PDIP)
Note: The control dimension is the inch column
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.160 0.015 0.125 0.014 0.030 0.008 1.380 0.600 0.485 MAX 0.250 0.070 0.195 0.024 0.070 0.014 1.565 0.625 0.580 MILLIMETERS MIN 4.06 0.38 3.18 0.36 0.76 0.20 35.05 15.24 12.32 MAX 6.35 1.78 4.95 0.56 1.78 0.38 39.75 15.88 14.73
0.100 BSC 0.600 BSC 0.600 0.115 0 0.700 0.200 15
2.54 BSC 15.24 BSC 15.24 2.92 0 17.78 5.08 15
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REV. 4.2.0
ST16C1450/51 2.97V TO 5.5V UART
PACKAGE DIMENSIONS (28 PIN PLCC)
Note: The control dimension is the inch column
INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.485 0.450 0.390 MAX 0.180 0.120 0.021 0.032 0.013 0.495 0.456 0.430 MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 12.32 11.43 9.91 MAX 4.57 3.05 0.53 0.81 0.32 12.57 11.58 10.92 7.62 typ. 1.27 BSC 1.07 1.07 0.64 1.42 1.22 1.14
0.300 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045
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ST16C1450/51 2.97V TO 5.5V UART
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REV. 4.2.0
REVISION HISTORY
Date
January 2003
Revision
Rev 4.0.0
Description
Changed to single column format. Clarified that the TX interrupt is not MS Windows compatible. Clarified timing diagrams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing symbols. Added TAH, TCS and OSC. Updated Ordering Information. Added Status Column to Ordering Information. Clarified compatibility to industry standard 16450 and MS Windows standard serial port driver in General Description. Removed Auto RTS flow control from MCR bit-1 description since that feature is not available in this device.
April 2003 September 2003 October 2003
Rev 4.0.1 Rev 4.1.0 Rev 4.2.0
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet October 2003. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
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2.97V TO 5.5VUART
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ST16C1450/51
REV. 4.2.0
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
FEATURES ..................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1 FIGURE 2. ST16C1450 PINOUTS ..................................................................................................................................................... 2 FIGURE 3. ST16C1451 PINOUTS ..................................................................................................................................................... 3 ORDERING INFORMATION ................................................................................................................................ 4
PIN DESCRIPTIONS ......................................................................................................... 5
DATA BUS INTERFACE ............................................................................................................................................. 5 MODEM OR SERIAL I/O INTERFACE ....................................................................................................................... 5 ANCILLARY SIGNALS ................................................................................................................................................ 6
1.0 PRODUCT DESCRIPTION .................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 7
2.1 INTERNAL REGISTERS ................................................................................................................................... 7 2.2 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK ......................................................................................... 8 2.3 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 8
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 8
2.4 TRANSMITTER ................................................................................................................................................. 9
2.4.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 9 2.4.2 TRANSMITTER OPERATION....................................................................................................................................... 9 TABLE 1: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ........................................................................ 9
2.5 RECEIVER ...................................................................................................................................................... 10
2.5.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 10 FIGURE 5. TRANSMITTER OPERATION ............................................................................................................................................. 10
2.6 SPECIAL (ENHANCED FEATURE) MODE ................................................................................................... 11
2.6.1 SOFT RESET .............................................................................................................................................................. 11 2.6.2 POWER DOWN MODE ............................................................................................................................................... 11
2.7
INTERNAL LOOPBACK ................................................................................................................................ 11
FIGURE 6. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 11 FIGURE 7. INTERNAL LOOPBACK..................................................................................................................................................... 12
3.0 UART INTERNAL REGISTERS ........................................................................................................... 13
TABLE 2: ST16C145X UART INTERNAL REGISTERS ............................................................................................................... 13 TABLE 3: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 14
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 15
4.1 4.2 4.3 4.4 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 15 15 15 15
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 16 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 16
4.5 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 16
TABLE 4: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 16
4.6 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 18
TABLE 5: PARITY SELECTION .......................................................................................................................................................... 18
4.7 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 19 4.8 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 20 4.9 SCRATCH PAD REGISTER (SPR) - READ/WRITE ...................................................................................... 21
TABLE 6: UART RESET CONDITIONS ........................................................................................................................................ 21
ABSOLUTE MAXIMUM RATINGS .................................................................................. 22
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: 15%) ................................................. 22
ELECTRICAL CHARACTERISTICS................................................................................ 22
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 22 AC ELECTRICAL CHARACTERISTICS.............................................................................................................. 23 TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V...................... 23
FIGURE 8. CLOCK TIMING............................................................................................................................................................... 24 FIGURE 9. MODEM INPUT/OUTPUT TIMING ...................................................................................................................................... 24 FIGURE 10. DATA BUS READ TIMING .............................................................................................................................................. 25 FIGURE 11. DATA BUS WRITE TIMING ............................................................................................................................................ 25
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REV. 4.2.0
2.97V TO 5.5VUART
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FIGURE 12. RECEIVE READY & INTERRUPT TIMING ......................................................................................................................... 26 FIGURE 13. TRANSMIT READY & INTERRUPT TIMING ....................................................................................................................... 26 PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM) ....................................................................................27 PACKAGE DIMENSIONS (28 PIN PDIP) ..........................................................................................................28 PACKAGE DIMENSIONS (28 PIN PLCC) .........................................................................................................29
REVISION HISTORY.......................................................................................................................................30 TABLE OF CONTENTS ............................................................................................................I
II

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